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X20C04 4K
X20C04
Nonvolatile Static RAM
512 x 8 Bit
FEATURES
DESCRIPTION
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM). The X20C04 is fabricated with advanced CMOS floating gate technology to achieve low power and wide power-supply margin. The X20C04 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs, ROMs, EPROMs, and E2PROMs. The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 5s or less. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.
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* * * * *
High Reliability --Endurance: 1,000,000 Nonvolatile Store Operations --Retention: 100 Years Minimum Power-on Recall --E2PROM Data Automatically Recalled Into SRAM Upon Power-up Lock Out Inadvertent Store Operations Low Power CMOS --Standby: 250A Infinite E2PROM Array Recall, and RAM Read and Write Cycles Compatible with X2004
PIN CONFIGURATION
PLASTIC CERDIP NC LCC PLCC VCC WE NE NC NC A7
NE NC A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 X20C04 21 20 19 18 17 16 15
VCC WE NC A8 NC NC OE NC CE I/O7 I/O6 I/O5 I/O4 I/O3
A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9
4
3
2
1 32 31 30 29 28 27 26 A8 NC NC NC OE NC CE I/O7 I/O6
X20C04 (TOP VIEW)
25 24 23 22
10 11 12
13 21 14 15 16 17 18 19 20
I/O1 I/O2 VSS NC I/O3 I/O4 I/O5
3825 FHD F02
3825 FHD F03
(c)Xicor, Inc. 1992, 1995, 1996 Patents Pending 3825-2.8 7/31/97 T4/C0/D0 SH
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Characteristics subject to change without notice
X20C04
PIN DESCRIPTIONS Addresses (A0-A8) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X20C04 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. Write Enable (WE) The Write Enable input controls the writing of data to both the static RAM and stores to the E2PROM. Nonvolatile Enable (NE) The Nonvolatile Enable input controls all accesses to the E2PROM array (store and recall functions). PIN NAMES Symbol A0-A8 I/O0-I/O7 WE CE OE NE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable Nonvolatile Enable +5V Ground No Connect
3825 PGM T01
FUNCTIONAL DIAGRAM
VCC SENSE EEPROM ARRAY
A3-A6
ROW SELECT
CE OE WE NE A0-A2 A7-A8 COLUMN SELECT & I/OS CONTROL LOGIC
I/O0-I/O7
ST O
R
E
512 x 8 SRAM ARRAY
R
EC
AL
L
3825 FHD F01
2
X20C04
DEVICE OPERATION The CE, OE, WE and NE inputs control the X20C04 operation. The X20C04 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C04. Nonvolatile Operations With NE LOW, recall operation is performed in the same manner as RAM read operation. A recall operation causes the entire contents of the E2PROM to be written into the RAM array. The time required for the operation to complete is 5s or less. A store operation causes the entire contents of the RAM array to be stored in the nonvolatile E2PROM. The time for the operation to complete is 5ms or less. Power-Up Recall Upon power-up (VCC), the X20C04 performs an automatic array recall. When VCC minimum is reached, the recall is initiated, regardless of the state of CE, OE, WE and NE. Write Protection The X20C04 has five write protect features that are employed to protect the contents of both the nonvolatile memory and the RAM. * VCC Sense--All functions are inhibited when VCC is 3.5V. * A RAM write is required before a Store Cycle is initiated. * Write Inhibit--Holding either OE LOW, WE HIGH, CE HIGH, or NE HIGH during power-up and powerdown will prevent an inadvertent store operation. * Noise Protection--A combined WE, NE, OE and CE pulse of less than 20ns will not initiate a Store Cycle. * Noise Protection--A combined WE, NE, OE and CE pulse of less than 20ns will not initiate a recall cycle. SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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X20C04
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. -65C to +135C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS ....................................... -1V to +7V D.C. Output Current ........................................... 10mA Lead Temperature (Soldering, 10 seconds) ..... 300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0C -40C -55C Max. +70C +85C +125C
3825 PGM T02.1
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage X20C04
Limits 5V 10%
3825 PGM T03
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol lCC1 Parameter VCC Current (Active) Min. Max. 100 Units mA Test Conditions NE = WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V levels @ f = 5MHz. All I/Os = Open All Inputs = VIH All I/Os = Open CE = VIH All Other Inputs = VIH, All I/Os = Open All Inputs = VCC - 0.3V All I/Os = Open VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH
ICC2 ISB1 ISB2 ILI ILO VIL(1) VIH(1) VOL VOH
VCC Current During Store VCC Standby Current (TTL Input) VCC Standby Current (CMOS Input) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage
10 10 250 10 10 0.8 VCC + 0.5 0.4
mA mA A A A V V V V
-1 2 2.4
IOL = 2.1mA IOH = -400A
3825 PGM T04.3
POWER-UP TIMING Symbol tPUR tPUW(2)
(2)
Parameter Power-Up to RAM Operation Power-Up to Nonvolatile Operation
Max. 100 5
Units s ms
3825 PGM T05
CAPACITANCE TA = +25C, F = 1MHz, VCC = 5V. Symbol CI/O(2) CIN(2) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V
3825 PGM T06.1
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
4
X20C04
ENDURANCE AND DATA RETENTION Parameter Endurance Store Cycles Data Retention MODE SELECTION CE H L L L L L L L L WE X H L L H L H L H NE X H H H L L H L L OE X L H H L H H L H Mode Not Selected Read RAM Write "1" RAM Write "0" RAM Array Recall Nonvolatile Storing Output Disabled Not Allowed No Operation I/O Output High Z Output Data Input Data High Input Data Low Output High Z Output High Z Output High Z Output High Z Output High Z Power Standby Active Active Active Active Active Active Active Active
3825 PGM T09.1
Min. 100,000 1,000,000 100
Units Data Changes Per Bit Store Cycles Years
3825 PGM T07.1
EQUIVALENT A.C. LOAD CIRCUIT
5V 1.92K OUTPUT 1.37K 100pF
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 10ns 1.5V
3825 PGM T08.2
3825 FHD F04.1
5
X20C04
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C04-15 Symbol tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Read Cycle
tRC ADDRESS tCE CE tOE OE VIH WE tOLZ tLZ DATA I/O DATA VALID tAA
3825 FHD F05
X20C04-20 X20C04-25 200 250 200 200 70 0 0 0 0 100 100 0 0 100 100 250 250 100
X20C04 300 300 300 150 0 0 100 100 0 ns ns ns ns ns ns ns ns ns
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold From Address Change
Min. Max. Min. Max. Min. Max. Min. Max. Units 150 150 150 50 0 0 80 80 0
3825 PGM T10
tOHZ tOH tHZ DATA VALID
Note:
(3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.
6
X20C04
Write Cycle Limits X20C04-15 Symbol tWC tCW tAS tWP tWR tDW tDH tWZ(4) tOW(4) tOZ(4) Parameter Write Cycle Time Chip Enable to End of Write Input Address Setup Time Write Pulse Width Write Recovery Time Data Setup to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write Output Enable to Output in High Z 150 150 0 100 0 100 0 80 5 80 5 100 X20C04-20 200 200 0 120 0 120 0 100 5 100 X20C04-25 250 250 0 150 0 150 0 100 5 100 X20C04 300 300 0 200 0 200 0 100 ns ns ns ns ns ns ns ns ns ns Min. Max. Min. Max. Min. Max. Min. Max. Units
3825 PGM T11
WE Controlled Write Cycle
tWC ADDRESS
OE tCW CE tAS WE tOZ DATA OUT tDW DATA IN DATA VALID
3825 FHD F06
tWP
tWR
tOW
tDH
Note:
(4) tWZ, tOW, and tOZ are periodically sampled and not 100% tested.
7
X20C04
CE Controlled Write Cycle
tWC ADDRESS
OE
VIH tCW
CE tAS WE tWZ DATA OUT tDW DATA IN DATA VALID tDH tOW tWP tWR
3825 FHD F07.1
8
X20C04
STORE CYCLE LIMITS X20C04-15 Symbol tSTC tSP tNHZ tOEST tSOE tNS Store Timing
tSTC tSP NE tSOE OE tOEST
X20C04-20 Min. 120 Max. 5
X20C04-25 Min. 150 Max. 5
X20C04 Min. 200 Max. 5 100 10 20 0 Units ms ns ns ns ns ns
3825 PGM T09
Parameter Store Cycle Time Store Pulse Width Nonvolatile Enable to Output in High Z Output Enable From End of Store OE Disable to Store Function NE Setup Time from WE
Min. 100
Max. 5 80
100 10 20 0 10 20 0
100
10 20 0
WE tNS CE tNHZ DATA I/O
VCC
VCC MIN (5)
3825 FHD F15.1
Note:
(5) X20C04 VCC min. = 4.5V The Store Pulse Width (tSP) is a minimum time that NE, WE and CE must be LOW simultaneously.
9
X20C04
ARRAY RECALL CYCLE LIMITS X20C04-15 Symbol tRCC tRCP(6) tRWE Parameter Array Recall Cycle Time Recall Pulse Width to InitiateRecall WE Setup Time to NE Min. 0.1 0 Max. 5 1 X20C04-20 Min. 0.12 0 Max. 5 1 X20C04-25 Min. 0.15 0 Max. 5 1 X20C04 Min. 0.2 0 Max. 5 1 Units s s ns
3825 PGM T13.1
Array Recall Cycle
tRCC ADDRESS tRCP NE
OE tRWE WE
CE
DATA I/O
3825 FHD F10
Note:
(6) The Recall Pulse Width (tRCP) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE.
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X20C04
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.490 (37.85) MAX.
0.610 (15.49) 0.500 (12.70)
PIN 1
0.005 (0.127) MIN. 0.100 (2.54) MAX.
SEATING PLANE
0.232 (5.90) MAX.
0.150 (3.81) MIN. 0.200 (5.08) 0.125 (3.18)
0.060 (1.52) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54)
0.065 (1.65) 0.038 (0.97) TYP. 0.055 (1.40)
0.023 (0.58) 0.014 (0.36) TYP. 0.018 (0.46)
0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60)
0.015 (0.38) 0.008 (0.20)
0 15
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F08
11
X20C04
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.470 (37.34) 1.400 (35.56)
0.557 (14.15) 0.510 (12.95) PIN 1 INDEX PIN 1 1.300 (33.02) REF. 0.085 (2.16) 0.040 (1.02)
SEATING PLANE 0.160 (4.06) 0.120 (3.05)
0.160 (4.06) 0.125 (3.17)
0.030 (0.76) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29)
0.065 (1.65) 0.040 (1.02)
0.022 (0.56) 0.014 (0.36)
0.625 (15.88) 0.590 (14.99)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F04
12
X20C04
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.300 (7.62) BSC 0.150 (3.81) BSC 0.015 (0.38) 0.003 (0.08) 0.020 (0.51) x 45 REF.
PIN 1
0.095 (2.41) 0.075 (1.91) 0.022 (0.56) DIA. 0.006 (0.15)
0.200 (5.08) BSC 0.015 (0.38) MIN. 0.028 (0.71) 0.022 (0.56) (32) PLCS.
0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS.
0.050 (1.27) BSC
0.040 (1.02) x 45 REF. TYP. (3) PLCS.
0.458 (11.63) 0.442 (11.22) 0.458 (11.63) -- 0.120 (3.05) 0.060 (1.52)
0.088 (2.24) 0.050 (1.27)
0.560 (14.22) 0.540 (13.71)
0.558 (14.17) --
0.400 (10.16) BSC
PIN 1 INDEX CORNER
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: 1% NLT 0.005 (0.127)
3926 FHD F14
13
X20C04
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050" TYPICAL
0.030" TYPICAL 32 PLACES
0.510" TYPICAL
0.050" TYPICAL
0.400"
0.050 (1.27) TYP.
FOOTPRINT
0.300" REF 0.410"
0.045 (1.14) x 45
0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43)
0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. PIN 1
SEATING PLANE 0.004 LEAD CO - PLANARITY -- 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07)
0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3 TYP.
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
14
X20C04
ORDERING INFORMATION X20C04 Device X X -X Access Time -15 = 150ns -20 = 200ns -25 = 250ns Blank = 300ns Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C MB = MIL-STD-833 Package D = 28-Lead Cerdip P = 28 Lead Plastic DIP E = 32-Pad Ceramic LCC J = 32-Lead PLCC
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.
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